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| integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. 00b 10/15/2012 copyright ? 2012 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b features ? internal self-timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and control ? burst sequence control using mode input ? three chip enable option for simple depth expan - sion and address pipelining ? common data inputs and data outputs ? auto power-down during deselect ? single cycle deselect ? snooze mode for reduced-power standby ? jtag boundary scan for pbga package ? power supply lf: v dd 3.3v ( + 5%), v ddq 3.3v/2.5v ( + 5%) vf: v dd 2.5v ( + 5%), v ddq 2.5v ( + 5%) vvf: v dd 1.8v ( + 5%), v ddq 1.8v ( + 5%) ? jedec 100-pin tqfp, 119-pin pbga, and 165- pin pbga packages ? lead-free available advanced information october 2012 2m x 36, 4m x 18 72 mb synchronous flow-through static ram description the 72mb product family features high-speed, low-power synchronous static rams designed to provide burstable, high-performance memory for communication and network - ing applications. the is61lf/vf204836b is organized as 2,096,952 words by 36 bits. the is61lf/vf409618b is organized as 4,193,904 words by 18 bits. fabricated with issi 's advanced cmos technology, the device integrates a 2-bit burst counter, high-speed sram core, and high- drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be writ - ten. byte write operation is performed by using byte write enable ( bwe ) input combined with one or more individual byte write signals ( bwx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be gener - ated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. inter - leave burst is achieved when this pin is tied high or left foating. fast access time symbol parameter -6.5 -7.5 units t kq clock access time 6.5 7.5 ns t kc cycle time 7.5 8.5 ns frequency 133 117 mhz
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b block diagram c l k / c k e / c e c e 2 / c e 2 / c e / c l r /ad v /ad s c /ad s p / g w / b w e / b w ( a - x ) x 18: x =b , x 32, x 36: x =d / c e c l k addres s reg i s t e r d q a 0 - x x 18: x = 21 x 36: x = 20 c l k d q ( a - d ) byt e w r i t e reg i s t e r s d q c l k enab l e reg i s t e r s d q / o e q 0 q 1 b i nary c o unt e r m o d e a 0 ` a 1 ` a 0 a 1 2mx 3 6 ; 4mx 1 8 m e m o r y a rray c l k i nput reg i s t e r c l k o u t put reg i s t e r d q ( a - x ) x 18: x = b , x 32, x 36: x = d powe r d o w n z z integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b bottom view bottom view 165-pin bga 165 -ball, 13x15 mm bga 165 -ball, 15x17 mm bga 1 mm ball pitch, 11 x 15 ball array 119-pin bga 119-ball, 14x22 mm bga 1.27 mm ball pitch, 7 x 17 ball array 4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b 119 bga package pin configuration 2m x 36 (top view) pin descriptions 1 2 3 4 5 6 7 a v ddq a a adsp a a v ddq b nc a a adsc a a nc c nc a a v dd a a nc d dqc dqpc vss nc vss dqpb dqb e dqc dqc vss ce vss dqb dqb f v ddq dqc vss oe vss dqb v ddq g dqc dqc bwc adv bwb dqb dqb h dqc dqc vss gw vss dqb dqb j v ddq v dd nc v dd nc v dd v ddq k dqd dqd vss clk vss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ddq dqd vss bwe vss dqa v ddq n dqd dqd vss a 1 * vss dqa dqa p dqd dqpd vss a 0 * vss dqpa dqa r nc a mode v dd nc a nc t nc a a a a a zz u v ddq tms tdi tck tdo nc v ddq symbol pin name a synchronous address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp synchronous address status processor adsc synchronous address status controller gw synchronous global write enable clk synchronous clock ce synchronous chip select bwa - bwd synchronous byte write controls bwe synchronous byte write enable symbol pin name oe a synchronous output enable zz a synchronous power sleep mode mode synchronous burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqd synchronous data inputs/outputs dqpa-dqpd synchronous parity data inputs/outputs v dd power supply v ddq i/o power supply vss ground note: * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b 119 bga package pin configuration 4m x 18 (top view) pin descriptions note: * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 a v ddq a a adsp a a v ddq b nc a a adsc a a nc c nc a a v dd a a nc d dqb nc vss nc vss dqpa nc e nc dqb vss ce vss nc dqa f v ddq nc vss oe vss dqa v ddq g nc dqb bwb adv vss nc dqa h dqb nc vss gw vss dqa nc j v ddq v dd nc v dd nc v dd v ddq k nc dqb vss clk vss nc dqa l dqb nc vss nc bwa dqa nc m v ddq dqb vss bwe vss nc v ddq n dqb nc vss a 1 * vss dqa nc p nc dqpb vss a 0 * vss nc dqa r nc a mode v dd nc a nc t a a a nc a a zz u v ddq tms tdi tck tdo nc v ddq symbol pin name a synchronous address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp synchronous address status processor adsc synchronous address status controller gw synchronous global write enable clk synchronous clock ce synchronous chip select bwa - bwb synchronous byte write controls bwe synchronous byte write enable symbol pin name oe a synchronous output enable zz asynchronous power sleep mode mode synchronous burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqb synchronous data inputs/outputs dqpa-dqpb synchronous parity data inputs/outputs v dd power supply v ddq i/o power supply vss ground 6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b pin descriptions 165 pbga package pin configuration 2m x 36 (top view) note: * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwc bwb ce2 bwe adsc adv a nc b nc a ce2 bwd bwa clk gw oe adsp a nc c dqpc nc v ddq vss vss vss vss vss v ddq nc dqpb d dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb e dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb f dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb g dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb h nc nc nc v dd vss vss vss v dd nc nc zz j dqd dqd v ddq v dd vss vss vss v dd v ddq dq a dq a k dqd dqd v ddq v dd vss vss vss v dd v ddq dq a dq a l dqd dqd v ddq v dd vss vss vss v dd v ddq dq a dq a m dqd dqd v ddq v dd vss vss vss v dd v ddq dq a dq a n dqpd nc v ddq vss nc a nc vss v ddq nc dqpa p nc a a a tdi a 1 * tdo a a a a r mode a a a tms a 0 * tck a a a a symbol pin name a synchronous address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp synchronous address status processor adsc synchronous address status controller gw synchronous global write enable clk synchronous clock ce , ce2 , ce2 synchronous chip select bwa - bwd synchronous byte write controls symbol pin name bwe synchronous byte write enable oe a synchronous output enable zz asynchronous power sleep mode mode synchronous burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqd synchronous data inputs/outputs dqpa-dqpd synchronous data inputs/outputs v dd power supply v ddq i/o power supply vss ground integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b note: * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. 165 pbga package pin configuration 4m x 18 (top view) pin descriptions 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwb nc ce2 bwe adsc adv a a b nc a ce2 nc bwa clk gw oe adsp a nc c nc nc v ddq vss vss vss vss vss v ddq nc dqpa d nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa e nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa f nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa g nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa h nc nc nc v dd vss vss vss v dd nc nc zz j dqb nc v ddq v dd vss vss vss v dd v ddq dq a nc k dqb nc v ddq v dd vss vss vss v dd v ddq dq a nc l dqb nc v ddq v dd vss vss vss v dd v ddq dq a nc m dqb nc v ddq v dd vss vss vss v dd v ddq dq a nc n dqpb nc v ddq vss nc a nc vss v ddq nc nc p nc a a a tdi a 1 * tdo a a a a r mode a a a tms a 0 * tck a a a a symbol pin name a synchronous address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp synchronous address status processor adsc synchronous address status controller gw synchronous global write enable clk synchronous clock ce , ce2 , ce2 synchronous chip select bwa - bwb synchronous byte write controls symbol pin name bwe synchronous byte write enable oe a synchronous output enable zz asynchronous power sleep mode mode synchronous burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqb synchronous data inputs/outputs dqpa-dqpb synchronous data inputs/outputs v dd power supply v ddq i/o power supply vss ground 8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b dqpb dqb dqb vddq vss dqb dqb dqb dqb vss vddq dqb dqb vss nc vdd zz dqa dqa vddq vss dqa dqa dqa dqa vss vddq dqa dqa dqpa a a ce ce2 bwd bwc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a dqpc dqc dqc vddq vss dqc dqc dqc dqc vss vddq dqc dqc nc vdd nc vss dqd dqd vddq vss dqd dqd dqd dqd vss vddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 a a vss vdd a a a a a a a a a 46 47 48 49 50 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs asc synchronous controller address status as synchronous processor address status synchronous burst address advance - synchronous byte write enable synchronous byte write enable , c2 , ce2 synchronous chip enable clk synchronous clock dqa-dqd synchronous data input/output dqpa-dqpd synchronous parity data input/output synchronous global write enable mode synchronous burst sequence mode selection asynchronous output enable v dd power supply v ddq i/o power supply vss ground zz asynchronous snooze enable pin configuration (3 chip-enable option) 100-pin tqfp (2m x 36) integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b pin configuration (3 chip-enable option) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwb synchronous byte write enable bwe synchronous byte write enable ce , ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqb synchronous data input/output dqpa-dqpb synchronous parity data input/output gw synchronous global write enable mode synchronous burst sequence mode selection oe asynchronous output enable v dd power supply v ddq i/o power supply vss ground zz asynchronous snooze enable 100-pin tqfp (4m x 18) a nc nc vddq vss nc dqpa dqa dqa vss vddq dqa dqa vss nc vdd zz dqa dqa vddq vss dqa dqa nc nc vss vddq nc nc nc a a ce ce2 nc nc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a nc nc nc vddq vss nc nc dqb dqb vss vddq dqb dqb nc vdd nc vss dqb dqb vddq vss dqb dqb dqpb nc vss vddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 a a vss vdd a a a a a a a a a 46 47 48 49 50 10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b partial truth table function gw bwe bwa bwb bwc bwd read h h x x x x read h l h h h h write byte 1 h l l h h h write all bytes h l l l l l write all bytes l x x x x x truth table (1-8) operation add ress ce ce2 ce2 zz adsp adsc adv w rite oe clk dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l x x x x l-h high-z deselect cycle, power-down none l h x l l x x x x l-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h x x x x x x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d note: 1. x means dont care. h means logic high. l means logic low. 2. for write , l means one or more byte write enable signals ( bwa-d ) and bwe are low or gw is low. write = h for all bwx , bwe , gw high. 3. bwa enables writes to dqas and dqpa. bwb enables writes to dqbs and dqpb. bwc enables writes to dqcs and dqpc. bwd enables writes to dqds and dqpd. dqpa and dqpb are available on the x18 version. dqpa-dqpd are avail - able on the x36 version. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. see write timing diagram for clarifcation. integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b interleaved burst address table (mode = v dd or no connect ) externa l address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = vss ) 0,0 1,0 0,1 a1', a0' = 1,1 power up sequence v ddq v dd 1 i/o pins 2 notes : 1. v dd can be applied at the same time as v ddq 2. a pplying i/o inputs is recommended after v ddq is ready. the inputs of the i/o pins can be applied at the same time as v ddq provided v ih (level of i/o pins) is lower than v ddq . power-up initialization timing vdd device initialization power > 1ms device ready fo r normal operatio n vdd vddq 12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b absolute maximum ratings (1) symbol parameter lf value vf/vvf value unit t stg storage temperature C55 to +150 C55 to +150 c p d power dissipation 1.6 1.6 w i out output current (per i/o) 100 100 ma v in , v out voltage relative to vss for i/o pins C0.5 to v ddq + 0.5 C0.5 to v ddq + 0.3 v v in voltage relative to vss for C0.5 to v dd + 0.5 C0.5 to v dd + 0.3 v for address and control inputs v dd voltage on v dd supply relative to vss C0.5 to v dd + 0.5 C0.3 to v dd + 0.3 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuitry to protect the inputs against damage due to high static voltages or electric felds; however, pre - cautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. operating range (is61lfxxxxx) range ambient temperature v dd v ddq commercial 0c to +70c 3.3v 5% 3.3v/2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v/2.5v 5% operating range (is61vfxxxxx) range ambient temperature v dd v ddq commercial 0c to +70c 2.5v 5% 2.5v 5% industrial -40c to +85c 2.5v 5% 2.5v 5% operating range (is61vvfxxxxx) range ambient temperature v dd v ddq commercial 0c to +70c 1.8v 5% 1.8v 5% industrial -40c to +85c 1.8v 5% 1.8v 5% integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b power supply characteristics (1) (over operating range) 6.5 7.5 max max symbol parameter test conditions temp. range x18 x36 x18 x36 uni t i cc ac operating device selected, com. 260 260 240 240 ma supply current oe = v ih , zz v il , ind. 270 270 250 250 all inputs 0.2v or v dd C 0.2v, cycle time t kc min. i sb standby current device deselected, com. 130 130 130 130 ma ttl input v dd = max., ind. 135 135 135 135 all inputs v il or v ih , zz v il , f = max. i sbi standby current device deselected, com. 115 115 115 115 m a c mos input v dd = max., ind. 120 120 120 120 v in v ss + 0.2v or v dd C 0.2v f = 0 dc electrical characteristics (over operating range) 1, 2, 3 3.3v 2.5v 1.8v symbol parameter test conditions min. max. min. max. min. max. unit v oh output high voltage i oh = C4.0 ma ( 3.3v) 2.4 2.0 v ddq - 0.4 v i oh = C1.0 ma (2.5v, 1.8v) v ol output low voltage i ol = 8.0 ma ( 3.3v) 0.4 0.4 0.4 v i ol = 1.0 ma (2.5v, 1.8v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 0.6v dd v dd + 0.3 v v il input low voltage C0.3 0.8 C0.3 0.7 C0.3 0.3v dd v i li input leakage current v ss v in v dd (1,4) C5 5 C5 5 C5 5 a input current of mode v ss v in v dd (5) C30 5 C30 5 C30 5 input current of zz v ss v in v dd (6) C5 30 C5 30 C5 30 i lo output leakage current v ss v out v ddq , oe = v ih C5 5 C5 5 C5 5 a notes: 1. all voltages referenced to ground. 2. overshoot: 3.3v and 2.5v: v ih (ac) v dd + 1.5v (pulse width less than t kc /2) 1.8v: v ih (ac) v dd + 0.5v (pulse width less than t kc /2) 3. undershoot: 3.3v and 2.5v: v il (ac) -1.5v (pulse width less than t kc /2) 1.8v: v il (ac) -0.5v (pulse width less than t kc /2) 4. except mode and zz 5. mode is connected to pull-up resister internally. 6. zz is connected to pull-down resister internally. 14 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b capacitance (1,2) sy mbol parameter condition s max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 3.3v i/o ac test conditions param eter u nit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 figure 2 317 5 pf including jig and scope 351 output 3.3v figure 1 output z o = 50 1.5v 50 ac test loads integrated silicon solution, inc. www.issi.com 1-800-379-4774 15 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 1.25v 50 output 1,667 5 pf including jig and scope 1,538 output +2.5v figure 3 figure 4 2.5v i/o output load equivalent 1.8v i/o ac test conditions parameter unit input pulse level 0v to 1.8v input rise and fall times 1.5 ns input and output timing 0.9v and reference level output load see figures 5 and 6 z o = 50 0.9v 50 output 1k 5 pf including jig and scope 1k output +1.8v figure 5 figure 6 1.8v i/o output load equivalent 16 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b read/write cycle switching characteristics (1) (over operating range) 6.5 7.5 symbol parameter min. max. min. max. unit fmax clock frequency 133 117 mhz t kc cycle time 7.5 8.5 ns t kh clock high time 2.2 2.5 ns t kl clock low time 2.2 2.5 ns t kq clock access time 6.5 7.5 ns t kqx (2) clock high to output invalid 2.5 2.5 ns t kqlz (2,3) clock high to output low-z 2.5 2.5 ns t kqhz (2,3) clock high to output high-z 3.8 4.0 ns t oeq output enable to output valid 3.2 3.4 ns t oelz (2,3) output enable to output low-z 0 0 ns t oehz (2,3) output disable to output high-z 3.5 3.5 ns t as address setup time 1.5 1.5 ns t ss address status setup time 1.5 1.5 ns t ws read/write setup time 1.5 1.5 ns t ces chip enable setup time 1.5 1.5 ns t av s address advance setup time 1.5 1.5 ns t ds data setup time 1.5 1.5 ns t ah address hold time 0.5 0.5 ns t sh address status hold time 0.5 0.5 ns t wh write hold time 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 ns t av h address advance hold time 0.5 0.5 ns t dh data hold time 0.5 0.5 ns t power (4) v dd (typical) to first access 1 1 ms notes: 1. confguration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2. 4. t power is the time that the power needs to be supplied above v dd (min) initially before read or write operation can be initiated. integrated silicon solution, inc. www.issi.com 1-800-379-4774 17 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b read/write cycle timing single read flow-through single write high-z high-z data out data in oe ce2 ce2 ce bwd-bwa bwe gw address adv adsc adsp clk rd1 wr1 wr1 1a 1a 2a 2b 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh adsp is blocked by ce inactive t ss t sh t as t ah t ws t wh t ws t wh t ws t wh rd2 rd3 t ces t ceh t ces t ceh t ces t ceh t oeq t oelz ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t kq t oehz t ds t dh t kqhz t kqlz high-z t kqlz t kq t kqx 18 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b write cycle timing single write data out data in oe ce2 ce2 ce bwd-bwa bwe gw address adv adsc adsp clk wr1w r2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce1 inactive t avh t avs adv must be inactive for adsp write wr1w r2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr 2 write 2c 2d 2b 2a integrated silicon solution, inc. www.issi.com 1-800-379-4774 19 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b snooze mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (e xcept zz) outputs (q) i sb2 zz setup cycle zz reco ve ry cycle nor mal operation cycle t pds t pus t zzi high-z snooze mode electrical characteristics symbol parameter conditions temp. range min. max. unit i sb 2 current during snooze mode zz v dd - 0.2v com. 80 ma ind. 90 auto. 100 t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to snooze current 2 cycle t rzzi zz inactive to exit snooze current 0 ns 20 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b ieee 1149.1 serial boundary scan (jtag) the serial boundary scan test access port (tap) is only available in the pbga package. this port operates in ac - cordance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specifcation are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not confict with the performance of other devices using 1149.1 fully compliant taps. disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (vss) to prevent clocking of the device. tdi and tms are internally pulled up and may be disconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left disconnected. on power-up, the device will start in a reset state which will not interfere with the device operation. test access port (tap) - test clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any regis - ter. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an applica - tion. tdi is connected to the most signifcant bit (msb) on any register. 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms tap controller block diagram integrated silicon solution, inc. www.issi.com 1-800-379-4774 21 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the cur - rent state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least signifcant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for fve rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the in - struction register. this register is loaded when it is placed between the tdi and tdo pins. (see tap controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the capture-ir state, the two least signifcant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass reg - ister is set low (vss) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 confguration has a 75-bit-long register and the x18 confguration also has a 75-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and then placed be - tween the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample-z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identifcation (id) register the id register is loaded with a vendor-specifc, 32-bit code during the capture-dr state when the idcode com - mand is loaded to the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has vendor code and other information described in the identifcation register defnitions table. scan register sizes register name bit size bi t size (x18) (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan 75 75 identification register definitions i nstruction field description 2m x 36 4m x 18 revision number (31:28) reserved for version number. xxxx xxxx device depth (27:23) defnes depth of sram. 2m or 4m 01010 01011 device width (22:18) defnes with of the sram. x36 or x18 00100 00011 issi device id (17:12) reserved for future use. xxxxx xxxxx issi jedec id (11:1) allows unique identifcation of sram vendor. 00001010101 00001010101 id register presence (0) indicate the presence of an id register. 1 1 22 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b tap instruction set eight instructions are possible with the three-bit instruction register and all combinations are listed in the instruction code table. three instructions are listed as reserved and should not be used and the other fve instructions are described below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals and cannot preload the input or output buf - fers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/ preload ; instead it performs a capture of the inputs and output ring when these instructions are executed. instruc - tions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap control - ler must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. because extest is not implemented in the tap controller, this device is not 1149.1 standard compliant. the tap controller recognizes an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is a difference between the instruc - tions, unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specifc, 32- bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample-z the sample-z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded to the instruc - tion register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock oper - ates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. because of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under-go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabilized long enough to meet the tap controllers capture set-up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/preload instruction. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk and clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update- dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruc - tion register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions. integrated silicon solution, inc. www.issi.com 1-800-379-4774 23 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b instruction codes code instruction description 000 extest captures the input/output ring contents. places the boundary scan register be - tween the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. 001 idcode loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. 010 sample-z captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. 011 reserved do not use: this instruction is reserved for future use. 100 sample/preload captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 reserved do not use: this instruction is reserved for future use. 110 reserved do not use: this instruction is reserved for future use. 111 bypass places the bypass register between tdi and tdo. this operation does not affect sram operation. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10 tap controller state diagram 24 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b tap electrical characteristics (v ddq = 1.8v operating range) symbol parameter test conditions min. max. units v oh 1 output high voltage i oh = -1.0 ma v dd -0.4 v v ol 1 output low voltage i ol = 1.0 ma 0.5 v v ih input high voltage 1.3 v dd +0.3 v v il input low voltage -0.3 0.7 v i x input load current vss v i v ddq -30 30 m a tap electrical characteristics (v ddq = 3.3v operating range) symbol parameter test conditions min. max. units v oh 1 output high voltage i oh = -4 ma 2.4 v v oh 2 output high voltage i oh = -100 a 2.9 v v ol 1 output low voltage i ol = 8 ma 0.4 v v ol 2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 2.0 v dd +0.3 v v il input low voltage C0.3 0.8 v i x input load current vss v in v ddq C30 30 m a tap electrical characteristics (v ddq = 2.5v operating range) symbol parameter test conditions min. max. units v oh 1 output high voltage i oh = -1 ma 2.0 v v oh 2 output high voltage i oh = -100 a 2.1 v v ol 1 output low voltage i ol = 1 ma 0.4 v v ol 2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage -0.3 0.7 v i x input load current vss v in v ddq C30 30 m a integrated silicon solution, inc. www.issi.com 1-800-379-4774 25 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b don't care undefined tck tms tdi tdo t thtl t tl th t thth t mvth t thmx t d vth t thdx 1 2 3 4 5 6 t tlo x t tlo v tap timing 20 pf tdo gnd 50 1.25v/1.5v z 0 = 50 tap output load equivalent tap ac test conditions (1.8v/2.5v/3.3v) input pulse levels 0 to 1.8v/0 to 2.5v/0 to 3.0v input rise and fall times 1.5ns input timing reference levels 0.9v/1.25v/1.5v output reference levels 0.9v/1.25v/1.5v test load termination supply voltage 0.9v/1.25v/1.5v parameter symbol min max units tck cycle time t thth 100 C ns tck high pulse width t thtl 40 C ns tck low pulse width t tlth 40 C ns tms setup t mvth 10 C ns tms hold t thmx 10 C ns tdi setup t dvth 10 C ns tdi hold t thdx 10 C ns tck low to valid data t tlov C 20 ns tap ac electrical characteristics (over operating range) 26 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b boundary scan order continued on next page 165 bga 119 bga x36 x18 x36 x18 bit # bump id signal bump id signal bit # bump id signal bump id signal 1 n6 a9 n6 a9 1 nc nc 2 n7 nc n7 nc 2 nc nc 3 n10 nc n10 nc 3 nc nc 4 p11 a8 p11 a8 4 nc nc 5 p8 a18 p8 a18 5 a18 a18 6 r8 a17 r8 a17 6 a17 a17 7 r9 a16 r9 a16 7 a16 a16 8 p9 a15 p9 a15 8 a15 a15 9 p10 a14 p10 a14 9 a14 a14 10 r10 a13 r10 a13 10 a13 a13 11 r11 a12 r11 a12 11 a12 a12 12 h11 zz h11 zz 12 t7 zz t7 zz 13 n11 dqa0 n11 nc 13 p6 dqa0 p6 nc 14 m11 dqa1 m11 nc 14 n7 dqa1 n7 nc 15 l11 dqa2 l11 nc 15 m6 dqa2 m6 nc 16 k11 dqa6 k11 nc 16 l7 dqa6 l7 nc 17 j11 dqa7 j11 nc 17 k6 dqa7 k6 nc 18 m10 dqa3 m10 dqa8 18 p7 dqa3 p7 dqa8 19 l10 dqa4 l10 dqa7 19 n6 dqa4 n6 dqa7 20 k10 dqa5 k10 dqa6 20 l6 dqa5 l6 dqa6 21 j10 dqa8 j10 dqa5 21 k7 dqa8 k7 dqa5 22 h9 nc h9 nc 22 nc nc 23 h10 nc h10 nc 23 nc nc 24 g11 dqb8 g11 dqa4 24 h6 dqb8 h6 dqa4 25 f11 dqb7 f11 dqa3 25 g7 dqb7 g7 dqa3 26 e11 dqb5 e11 dqa2 26 f6 dqb5 f6 dqa2 27 d11 dqb4 d11 dqa1 27 e7 dqb4 e7 dqa1 28 g10 dqb6 g10 nc 28 h7 dqb6 h7 nc 29 f10 dqb3 f10 nc 29 g6 dqb3 g6 nc 30 e10 dqb2 e10 nc 30 e6 dqb2 e6 nc 31 d10 dqb1 d10 nc 31 d7 dqb1 d7 nc 32 c11 dqb0 c11 dqa0 32 d6 dqb0 d6 dqa0 33 a11 nc a11 a21 33 t1 nc t1 a21 34 b11 nc b11 nc 34 nc nc 35 a10 a11 a10 a11 35 a11 a11 36 b10 a10 b10 a10 36 a10 a10 37 a9 /adv a9 /adv 37 g4 /adv g4 /adv 38 b9 /adsp b9 /adsp 38 a4 /adsp a4 /adsp 39 c10 nc c10 nc 39 nc nc 40 a8 /adsc a8 /adsc 40 b4 /adsc b4 /adsc 41 b8 /oe b8 /oe 41 f4 /oe f4 /oe 42 a7 /bwe a7 /bwe 42 m4 /bwe m4 /bwe 43 b7 /gw b7 /gw 43 h4 /gw h4 /gw 44 b6 clk b6 clk 44 k4 clk k4 clk integrated silicon solution, inc. www.issi.com 1-800-379-4774 27 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b 165 bga 119 bga x36 x18 x36 x18 bit # bump id signal bump id signal bit # bump id signal bump id signal 45 a6 /ce2 a6 /ce2 45 b6 a9 b6 a9 46 b5 /bwa b5 /bwa 46 l5 /bwa l5 /bwa 47 a5 /bwb a5 nc 47 g5 /bwb g5 nc 48 a4 /bwc a4 /bwb 48 g3 /bwc g3 /bwb 49 b4 /bwd b4 nc 49 l3 /bwd l3 nc 50 b3 ce2 b3 ce2 50 b2 a8 b2 a8 51 a3 /ce1 a3 /ce1 51 e4 /ce1 e4 /ce1 52 a2 a7 a2 a7 52 a7 a7 53 b2 a6 b2 a6 53 a6 a6 54 c2 nc c2 nc 54 nc nc 55 b1 nc b1 nc 55 nc nc 56 a1 nc a1 nc 56 nc nc 57 c1 dqc0 c1 nc 57 d2 dqc0 d2 nc 58 d1 dqc1 d1 nc 58 e1 dqc1 e1 nc 59 e1 dqc2 e1 nc 59 f2 dqc2 f2 nc 60 f1 dqc6 f1 nc 60 g1 dqc6 g1 nc 61 g1 dqc7 g1 nc 61 h2 dqc7 h2 nc 62 d2 dqc3 d2 dqb8 62 d1 dqc3 d1 dqb8 63 e2 dqc4 e2 dqb7 63 e2 dqc4 e2 dqb7 64 f2 dqc5 f2 dqb6 64 g2 dqc5 g2 dqb6 65 g2 dqc8 g2 dqb5 65 h1 dqc8 h1 dqb5 66 h1 nc h1 nc 66 nc nc 67 h2 nc h2 nc 67 nc nc 68 h3 nc h3 nc 68 nc nc 69 j1 dqd8 j1 dqb4 69 k2 dqd8 k2 dqb4 70 k1 dqd7 k1 dqb3 70 l1 dqd7 l1 dqb3 71 l1 dqd5 l1 dqb2 71 m2 dqd5 m2 dqb2 72 m1 dqd4 m1 dqb1 72 n1 dqd4 n1 dqb1 73 j2 dqd6 j2 nc 73 k1 dqd6 k1 nc 74 k2 dqd3 k2 nc 74 l2 dqd3 l2 nc 75 l2 dqd2 l2 nc 75 n2 dqd2 n2 nc 76 m2 dqd1 m2 nc 76 p1 dqd1 p1 nc 77 n1 dqd0 n1 dqb0 77 p2 dqd0 p2 dqb0 78 n2 nc n2 nc 78 nc nc 79 p1 nc p1 nc 79 nc nc 80 r1 mode r1 mode 80 r3 mode r3 mode 81 r2 a4 r2 a4 81 a4 a4 82 p3 a3 p3 a3 82 a3 a3 83 r3 a2 r3 a2 83 a2 a2 84 p2 a5 p2 a5 84 a5 a5 85 r4 a19 r4 a19 85 a19 a19 86 p4 a20 p4 a20 86 t2 a20 t2 a20 87 n5 nc n5 nc 87 nc nc 88 p6 a1 p6 a1 88 n4 a1 n4 a1 89 r6 a0 r6 a0 89 p4 a0 p4 a0 90 * int * int 90 * int * int 28 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b access time x36 x18 package 6.5ns IS61LF204836B-6.5tq is61lf409618b-6.5tq 100 tqfp IS61LF204836B-6.5b3 is61lf409618b-6.5b3 165 pbga,13x15mm IS61LF204836B-6.5m3 is61lf409618b-6.5m3 165 pbga,15x17mm IS61LF204836B-6.5b2 is61lf409618b-6.5b2 119 pbga IS61LF204836B-6.5tql is61lf409618b-6.5tql 100 tqfp, lead-free IS61LF204836B-6.5b3l is61lf409618b-6.5b3l 165 pbga,13x15mm, lead-free IS61LF204836B-6.5m3l is61lf409618b-6.5m3l 165 pbga,15x17mm, lead-free IS61LF204836B-6.5b2l is61lf409618b-6.5b2l 119 pbga, lead-free 7.5ns IS61LF204836B-7.5tq is61lf409618b-7.5tq 100 tqfp IS61LF204836B-7.5b3 is61lf409618b-7.5b3 165 pbga,13x15mm IS61LF204836B-7.5m3 is61lf409618b-7.5m3 165 pbga,15x17mm IS61LF204836B-7.5b2 is61lf409618b-7.5b2 119 pbga IS61LF204836B-7.5tql is61lf409618b-7.5tql 100 tqfp, lead-free IS61LF204836B-7.5b3l is61lf409618b-7.5b3l 165 pbga,13x15mm, lead-free IS61LF204836B-7.5m3l is61lf409618b-7.5m3l 165 pbga,15x17mm, lead-free IS61LF204836B-7.5b2l is61lf409618b-7.5b2l 119 pbga, lead-free commercial range: 0c to 70c (vdd = 2.5v / vddq = 2.5v) access time x36 x18 package 6.5ns is61vf204836b-6.5tq is61vf409618b-6.5tq 100 tqfp is61vf204836b-6.5b3 is61vf409618b-6.5b3 165 pbga,13x15mm is61vf204836b-6.5m3 is61vf409618b-6.5m3 165 pbga,15x17mm is61vf204836b-6.5b2 is61vf409618b-6.5b2 119 pbga is61vf204836b-6.5tql is61vf409618b-6.5tql 100 tqfp, lead-free is61vf204836b-6.5b3l is61vf409618b-6.5b3l 165 pbga,13x15mm, lead-free is61vf204836b-6.5m3l is61vf409618b-6.5m3l 165 pbga,15x17mm, lead-free is61vf204836b-6.5b2l is61vf409618b-6.5b2l 119 pbga, lead-free 7.5ns is61vf204836b-7.5tq is61vf409618b-7.5tq 100 tqfp is61vf204836b-7.5b3 is61vf409618b-7.5b3 165 pbga,13x15mm is61vf204836b-7.5m3 is61vf409618b-7.5m3 165 pbga,15x17mm is61vf204836b-7.5b2 is61vf409618b-7.5b2 119 pbga is61vf204836b-7.5tql is61vf409618b-7.5tql 100 tqfp, lead-free is61vf204836b-7.5b3l is61vf409618b-7.5b3l 165 pbga,13x15mm, lead-free is61vf204836b-7.5m3l is61vf409618b-7.5m3l 165 pbga,15x17mm, lead-free is61vf204836b-7.5b2l is61vf409618b-7.5b2l 119 pbga, lead-free commercial range: 0c to 70c(vdd = 3.3v / vddq = 2.5v/3.3v) ordering information integrated silicon solution, inc. www.issi.com 1-800-379-4774 29 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b commercial range: 0c to 70c(vdd = 1.8v / vddq = 1.8v) access time x36 x18 package 7.5ns is61vvf204836b-7.5tq is61vvf409618b-7.5tq 100 tqfp is61vvf204836b-7.5b3 is61vvf409618b-7.5b3 165 pbga,13x15mm is61vvf204836b-7.5m3 is61vvf409618b-7.5m3 165 pbga,15x17mm is61vvf204836b-7.5b2 is61vvf409618b-7.5b2 119 pbga is61vvf204836b-7.5tql is61vvf409618b-7.5tql 100 tqfp, lead-free is61vvf204836b-7.5b3l is61vvf409618b-7.5b3l 165 pbga,13x15mm, lead-free is61vvf204836b-7.5m3l is61vvf409618b-7.5m3l 165 pbga,15x17mm, lead-free is61vvf204836b-7.5b2l is61vvf409618b-7.5b2l 119 pbga, lead-free access time x36 x18 package 6.5ns IS61LF204836B-6.5tqi is61lf409618b-6.5tqi 100 tqfp IS61LF204836B-6.5b3i is61lf409618b-6.5b3i 165 pbga,13x15mm IS61LF204836B-6.5m3i is61lf409618b-6.5m3i 165 pbga,15x17mm IS61LF204836B-6.5b2i is61lf409618b-6.5b2i 119 pbga IS61LF204836B-6.5tqli is61lf409618b-6.5tqli 100 tqfp, lead-free IS61LF204836B-6.5b3li is61lf409618b-6.5b3li 165 pbga,13x15mm, lead-free IS61LF204836B-6.5m3li is61lf409618b-6.5m3li 165 pbga,15x17mm, lead-free IS61LF204836B-6.5b2li is61lf409618b-6.5b2li 119 pbga, lead-free 7.5ns IS61LF204836B-7.5tqi is61lf409618b-7.5tqi 100 tqfp IS61LF204836B-7.5b3i is61lf409618b-7.5b3i 165 pbga,13x15mm IS61LF204836B-7.5m3i is61lf409618b-7.5m3i 165 pbga,15x17mm IS61LF204836B-7.5b2i is61lf409618b-7.5b2i 119 pbga IS61LF204836B-7.5tqli is61lf409618b-7.5tqli 100 tqfp, lead-free IS61LF204836B-7.5b3li is61lf409618b-7.5b3li 165 pbga,13x15mm, lead-free IS61LF204836B-7.5m3li is61lf409618b-7.5m3li 165 pbga,15x17mm, lead-free IS61LF204836B-7.5b2li is61lf409618b-7.5b2li 119 pbga, lead-free industrial range: -40c to +85c (vdd = 3.3v / vddq = 2.5v/3.3v) 30 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b industrial range: -40c to +85c (vdd = 2.5v / vddq = 2.5v) access time x36 x18 package 6.5ns is61vf204836b-6.5tqi is61vf409618b-6.5tqi 100 tqfp is61vf204836b-6.5b3i is61vf409618b-6.5b3i 165 pbga,13x15mm is61vf204836b-6.5m3i is61vf409618b-6.5m3i 165 pbga,15x17mm is61vf204836b-6.5b2i is61vf409618b-6.5b2i 119 pbga is61vf204836b-6.5tqli is61vf409618b-6.5tqli 100 tqfp, lead-free is61vf204836b-6.5b3li is61vf409618b-6.5b3li 165 pbga,13x15mm, lead-free is61vf204836b-6.5m3li is61vf409618b-6.5m3li 165 pbga,15x17mm, lead-free is61vf204836b-6.5b2li is61vf409618b-6.5b2li 119 pbga, lead-free 7.5ns is61vf204836b-7.5tqi is61vf409618b-7.5tqi 100 tqfp is61vf204836b-7.5b3i is61vf409618b-7.5b3i 165 pbga,13x15mm is61vf204836b-7.5m3i is61vf409618b-7.5m3i 165 pbga,15x17mm is61vf204836b-7.5b2i is61vf409618b-7.5b2i 119 pbga is61vf204836b-7.5tqli is61vf409618b-7.5tqli 100 tqfp, lead-free is61vf204836b-7.5b3li is61vf409618b-7.5b3li 165 pbga,13x15mm, lead-free is61vf204836b-7.5m3li is61vf409618b-7.5m3li 165 pbga,15x17mm, lead-free is61vf204836b-7.5b2li is61vf409618b-7.5b2li 119 pbga, lead-free industrial range: -40c to +85c (vdd = 1.8v / vddq = 1.8v) access time x36 x18 package 7.5ns is61vvf204836b-7.5tqi is61vvf409618b-7.5tqi 100 tqfp is61vvf204836b-7.5b3i is61vvf409618b-7.5b3i 165 pbga,13x15mm is61vvf204836b-7.5m3i is61vvf409618b-7.5m3i 165 pbga,15x17mm is61vvf204836b-7.5b2i is61vvf409618b-7.5b2i 119 pbga is61vvf204836b-7.5tqli is61vvf409618b-7.5tqli 100 tqfp, lead-free is61vvf204836b-7.5b3li is61vvf409618b-7.5b3li 165 pbga,13x15mm, lead-free is61vvf204836b-7.5m3li is61vvf409618b-7.5m3li 165 pbga,15x17mm, lead-free is61vvf204836b-7.5b2li is61vvf409618b-7.5b2li 119 pbga, lead-free automotive(a3) range: -40c to +125c (vdd = 3.3v / vddq = 2.5v/3.3v) access time x36 x18 package please contact issi sram@issi.com automotive(a3) range: -40c to +125c (vdd = 2.5v / vddq = 2.5v) access time x36 x18 package please contact issi sram@issi.com automotive(a3) range: -40c to +125c (vdd = 1.8v / vddq = 1.8v) access time x36 x18 package please contact issi sram@issi.com integrated silicon solution, inc. www.issi.com 1-800-379-4774 31 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b 32 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b integrated silicon solution, inc. www.issi.com 1-800-379-4774 33 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b 1. controlling dimension : mm . note : package outline 08/28/2008 34 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. 00b 10/15/2012 IS61LF204836B, is61vf/vvf204836b is61lf409618b, is61vf/vvf409618b note : 1. controlling dimension : mm package outline 12/10/2007 |
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